1. Technical Field
The present invention relates in general to the field of data processing, and, in particular, to an improved data processing system and method for handling interrupts.
2. Description of the Related Art
When executing a set of computer instructions, a processor is frequently interrupted. This interruption may be caused by an interrupt or an exception.
An interrupt is an asynchronous interruption event that is not associated with the instruction that is executing when the interrupt occurs. That is, the interruption is often caused by some event outside the processor, such as an input from an input/output (I/O) device, a call for an operation from another processor, etc. Other interrupts may be caused internally, for example, by the expiration of a timer that controls task switching.
An exception is a synchronous event that arises directly from the execution of the instruction that is executing when the exception occurs. That is, an exception is an event from within the processor, such as an arithmetic overflow, a timed maintenance check, an internal performance monitor, an on-board workload manager, etc. Typically, exceptions are far more frequent than interrupts.
The terms “interrupt” and “exception” are often interchanged. For the purposes of this disclosure, the term “interrupt” will be used to describe both “interrupt” and “exception” interruptions.
As computer software and hardware have become more complex, the number and frequency of interrupts has increased dramatically. These interrupts are necessary, in that they support the execution of multiple processes, handling of multiple peripherals, and performance monitoring of various components. While such features are beneficial, the consumption of computing power by interrupts is increasing so dramatically that it is outstripping processing speed improvements of the processor(s). Thus, in many cases system performance is actually decreasing in real terms despite increasing processor clock frequencies.
FIG. 1 illustrates a conventional processor core 100. Within processor core 100, a Level 1 Instruction cache (L1 J-cache) 102 provides instructions to instruction sequencing logic 104, which issues the instructions to the appropriate execution units 108 for execution. Execution units 108, which may include a floating point execution unit, a fixed point execution unit, a branch execution unit, etc., include a load/store unit (LSU) 108a. LSU 108a executes load and store instructions, which load data from Level 1 Data cache (L1 D-cache) 112 into architected register 110 and store data from architected register 110 to L1 D-cache 112, respectively. Requests for data and instructions that miss L1 caches 102 and 112 can be resolved by accessing system memory 118 via memory bus 116.
As noted above, processor core 100 is subject to interrupts from a number of sources represented by external interrupt lines 114. When an interrupt signal is received by processor core 100 (e.g., via one of the interrupt lines 114), execution of current process(es) are suspended and the interrupt is handled by interrupt-specific software known as an interrupt handler. Among other activities, the interrupt handler saves and restores the architected state of the process executing at the time of the interrupt through the execution of store and load instructions by LSU 108a. This use of LSU 108a to transfer the architected state to and from system memory 118 blocks execution of other memory access instructions by the interrupt handler, (or another process in the case of a superscalar computer) until the state transfer is complete. Consequently, saving and subsequently restoring the architected states of a process through the execution units of the processor causes a delay in execution of both the interrupted process as well as the interrupt handler. This delay results in a degradation of the overall performance of the processor. Thus, the present invention recognizes that there is a need for a method and system that minimize the processing delay incurred by saving and restoring architected states, particularly in response to interrupt.